Cache Coherence Protocols in Distributed Systems

Main Article Content

Hanan M. Shukur
Subhi Zeebaree
Rizgar R. Zebari
Omar M. Ahmed
Lailan M. Haji
Dildar M. Abdulqader

Abstract

Distributed systems performance is affected significantly by cache coherence protocols due to their role in data consistency maintaining. Also, cache coherent protocols have a great task for keeping the interconnection of caches in a multiprocessor environment. Moreover, the overall performance of distributed shared memory multiprocessor system is influenced by the used cache coherence protocol type. The major challenge of shared memory devices is to maintain the cache coherently. Therefore, in past years many contributions have been presented to address the cache issues and to improve the performance of distributed systems. This paper reviews in a systematic way a number of methods used for the cache-coherent protocols in a distributed system.

Article Details

How to Cite
[1]
H. Shukur, S. Zeebaree, R. Zebari, O. Ahmed, L. Haji, and D. Abdulqader, “Cache Coherence Protocols in Distributed Systems”, JASTT, vol. 1, no. 3, pp. 92 - 97, Jun. 2020.
Section
Articles

References

S. R. Zeebaree, L. M. Haji, I. Rashid, R. R. Zebari, O. M. Ahmed, K. Jacksi, & H. M. Shukur, “Multicomputer Multicore System Influence on Maximum Multi-Processes Execution Time,” TEST Engineering & Management, vol. 83, no. May/June, pp. 14921–14931, May 2020.

D. R. K. Ports, J. Li, V. Liu, N. K. Sharma, and A. Krishnamurthy, “Designing Distributed Systems Using Approximate Synchrony in Data Center Networks,” 2015, pp. 43–57, Accessed: Feb. 27, 2020. [Online]. Available: https://www.usenix.org/conference/nsdi15/technical-sessions/presentation/ports.

R. R. Zebari, S. R. Zeebaree, and K. Jacksi, “Impact Analysis of HTTP and SYN Flood DDoS Attacks on Apache 2 and IIS 10.0 Web Servers,” in 2018 International Conference on Advanced Science and Engineering (ICOASE), 2018, pp. 156–161.

O. H. Jader, S. R. Zeebaree, and R. R. Zebari, “A State Of Art Survey For Web Server Performance Measurement And Load Balancing Mechanisms,” INTERNATIONAL JOURNAL OF SCIENTIFIC & TECHNOLOGY RESEARCH, vol. 8, no. 12, pp. 535–543, Dec. 2019.

S. R. Zeebaree, R. R. Zebari, K. Jacksi, and D. A. Hasan, “Security Approaches For Integrated Enterprise Systems Performance: A Review,” International Journal of Scientific & Technology Research, vol. 8, no. 12, Dec. 2019.

G. Lu, J. Zhan, X. Lin, C. Tan, and L. Wang, “On Horizontal Decomposition of the Operating System,” CoRR abs/1604.01378, 2016.

L. M. Haji, S. R. Zeebaree, K. Jacksi, and D. Q. Zeebaree, “A State of Art Survey for OS Performance Improvement,” Science Journal of University of Zakho, vol. 6, no. 3, pp. 118–123, 2018.

Z. N. Rashid, S. R. Zebari, K. H. Sharif, and K. Jacksi, “Distributed Cloud Computing and Distributed Parallel Computing: A Review,” in 2018 International Conference on Advanced Science and Engineering (ICOASE), 2018, pp. 167–172.

S. R. M. Zeebaree, H. M. Shukur, L. M. Haji, R. R. Zebari, K. Jacksi, and S. M.Abas, “Characteristics and Analysis of Hadoop Distributed Systems,” Technology Reports of Kansai University, vol. 62, no. 4, pp. 1555–1564, Apr. 2020.

S. R. Zeebaree, R. R. Zebari, and K. Jacksi, “Performance analysis of IIS10.0 and Apache2 Cluster-based Web Servers under SYN DDoS Attack,” TEST Engineering & Management, vol. 83, no. March-April 2020, pp. 5854–5863, 2020.

S. Bansal, S. Sharma, and I. Trivedi, “A Detailed Review of Fault-Tolerance Techniques in Distributed System.,” International Journal on Internet & Distributed Computing Systems, vol. 1, no. 1, 2011.

K. Jacksi, “Design and Implementation of Online Submission And Peer Review System: A Case Study Of E-Journal Of University Of Zakho,” International Journal of Scientific & Technology Research, vol. 4, no. 8, pp. 83–85, 2015.

S. R. Zeebaree, K. F. Jacksi, and R. R. Zebari, “Impact analysis of SYN flood DDOS attack on HAPROXY and NLB cluster-base web servers,” Indonesian Journal of Electrical Engineering and Computer Science, vol. 19, no. 1, Art. no. 1, doi: 10.11591/ijeecs.v19.i1.pp. 505 - 512, 2020.

Z. Subhi RM and J. Karwan, “Effects of Processes Forcing on CPU and Total Execution-Time Using Multiprocessor Shared Memory System,” International Journal of Computer Engineering in Research Trends, vol. 2, no. 4, pp. 275-279, 2015.

R. R. Zebari, S. R. Zeebaree, K. Jacksi, and H. M. Shukur, “E-Business Requirements For Flexibility And Implementation Enterprise System: A Review,” International Journal of Scientific & Technology Research, vol. 8, no. 11, pp. 655–660, Nov. 2019.

R. Komuravelli, S. V. Adve, and C.-T. Chou, “Revisiting the complexity of hardware cache coherence and some implications,” ACM Transactions on Architecture and Code Optimization (TACO), vol. 11, no. 4, pp. 1–22, 2014.

N. B. Mallya, G. Patil, and B. Raveendran, “Simulation based Performance Study of Cache Coherence Protocols,” in 2015 IEEE International Symposium on Nanoelectronic and Information Systems, 2015, pp. 125–130.

O. Alzakholi, L. Haji, H. Shukur, R. Zebari, S. Abas, and M. Sadeeq, “Comparison Among Cloud Technologies and Cloud Performance,” Journal of Applied Science and Technology Trends, vol. 1, no. 2, Apr. 2020, doi: 10.38094/jastt1219.

A. Saparon and F. N. B. Razlan, “Cache Coherence Protocols in Multi-Processor,” in International conference on Computer Science and Information Systems (ICSIS), 2014, pp. 17–18, 2014.

X. Qin and P. Mishra, “Automated generation of directed tests for transition coverage in cache coherence protocols,” in 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2012, pp. 3–8.

Z. Al-Waisi and M. O. Agyeman, “An overview of on-chip cache coherence protocols,” in 2017 Intelligent Systems Conference (IntelliSys), 2017, pp. 304–309.

D. P. Kaur and V. Sulochana, “Design and Implementation of Cache Coherence Protocol for High-Speed Multiprocessor System,” in 2018 2nd IEEE International Conference on Power Electronics, Intelligent Control and Energy Systems (ICPEICES), 2018, pp. 1097–1102.

D. Kehagias and I. Raptis, “An Android-based MESI Cache Coherence Simulator.” in 2017, International Virtual Conference on Advanced Scientific Result, pp. 194–199.

C. Bernard, H.-N. Nguyen, E. Guthmuller, and Y. Durand, “Design and implementation of an In-Network Cache Coherence protocol,” in Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications (PDPTA), 2013, p. 298.

Quang, Vinh Ngo et al. “Exploring Cache Coherency Design for Chip Multiprocessor using Multi2Sim.” International Journal of Engineering Research and Technology 4 (2015), pp. 775 - 779.

S. Almakdi, A. Alazeb, and M. Alshehri, “Cache coherence mechanisms,” International journal of engineering and innovative technology, vol. 4, pp. 158 - 167, 2015.

F. L. Y. Team, X. K. Z. B. Y. Jiang, and C. Lou, “Robust Cache Coherence Protocol Verification with Inferno.”

Aghaei, Babak, and Negin Zaman-Zadeh. "Evaluation of Cache Coherence Protocols in terms of Power and Latency in Multiprocessors." In 3rd International Conference on Research in Engineering. 2016.

D. Kehagias, “Using two Educational Simulator Tools for Computer Architecture Teaching and Learning Support,” International Journal of Computer Applications, vol. 180, no. 47, pp. 8 - 12, 2018.

D. Smelt, “Modeling many-core processor interconnect scalability for the evolving performance, power and area relation,” 2018.

T. A. Eltaras, W. Fornaciari, D. Zoni, "Partial packet forwarding to improve performance in fully adaptive routing for cache-coherent nocs." In 2019 27th Euromicro International Conference on Parallel, Distributed and Network-Based Processing (PDP), 2019, pp. 33-40.

S. S. Prabhu, A. A. Kadar, and J. Simon, “Design and Development of Cache Coherent Interconnect based on ACE Protocol Specification.” International Journal of Engineering Research & Technology, vol. 8, pp. 730-734, 2019.

D. Deb, J. Jose, and M. Palesi, “ECAP: energy-efficient caching for prefetch blocks in tiled chip multiprocessors,” IET Computers & Digital Techniques, vol. 13, no. 6, pp. 417–428, 2019.

J. Li, L. Shi, C. J. Xue, and Y. Xu, “Thread progress aware coherence adaption for hybrid cache coherence protocols,” IEEE Transactions on Parallel and Distributed Systems, vol. 25, no. 10, pp. 2697–2707, 2013.

G. Mencagli, M. Vanneschi, and S. Lametti, “The home-forwarding mechanism to reduce the cache coherence overhead in next-generation CMPs,” Future Generation Computer Systems, vol. 82, pp. 493–509, 2018.

S. Sun, H. An, and J. Chen, “Cache Coherence Method for Improving Multi-threaded Applications on Multicore Systems,” in 2014 6th International Conference on Multimedia, Computer Graphics and Broadcasting, 2014, pp. 47–50.

J. Wang and D. Wang, “A smart protocol-level task mapping for energy efficient traffic on network-on-chip,” Microprocessors and Microsystems, vol. 65, pp. 69–78, 2019.

Most read articles by the same author(s)